PIC18F4450-I/PT【PDF 132/241 页】IC PIC MCU FLASH 8KX16 44TQFP

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217

XMEGA A [MANUAL]

8077I–AVR–11/2012

Reading the DATA register

Writing a valid command to the CMD bits in the CTRLC register

Bit 6

– WIF: Write Interrupt Flag

This flag is set when a byte is transmitted in master write mode. The flag is set regardless of the occurrence of a bus

error or an arbitration lost condition. WIF is also set if arbitration is lost during sending of a NACK in master read mode,

and if issuing a START condition when the bus state is unknown. Writing a one to this bit location will clear WIF. When

this flag is set, the master forces the SCL line low, stretching the TWI clock period. Clearing the interrupt flags will release

the SCL line.

The flag is also cleared automatically for the same conditions as RIF.

Bit 5

– CLKHOLD: Clock Hold

This flag is set when the master is holding the SCL line low. This is a status flag and a read-only flag that is set when RIF

or WIF is set. Clearing the interrupt flags and releasing the SCL line will indirectly clear this flag.

The flag is also cleared automatically for the same conditions as RIF.

Bit 4

– RXACK: Received Acknowledge

This flag contains the most recently received acknowledge bit from the slave. This is a read-only flag. When read as zero,

the most recent acknowledge bit from the slave was ACK, and when read as one the most recent acknowledge bit was

NACK.

Bit 3

– ARBLOST: Arbitration Lost

This flag is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a START or repeated

START condition on the bus. Writing a one to this bit location will clear ARBLOST.

Writing the ADDR register will automatically clear ARBLOST.

Bit 2

– BUSERR: Bus Error

This flag is set if an illegal bus condition has occurred. An illegal bus condition occurs if a repeated START or a STOP

condition is detected, and the number of received or transmitted bits from the previous START condition is not a multiple

of nine. Writing a one to this bit location will clear BUSERR.

Writing the ADDR register will automatically clear BUSERR.

Bit 1:0

– BUSSTATE[1:0]: Bus State

These bits indicate the current TWI bus state as defined in Table 19-5 on page 216. The change of bus state is

dependent on bus activity. Refer to the “TWI Bus State Logic” on page 209.

Table 19-6. TWI master bus state.

Writing 01 to the BUSSTATE bits forces the bus state logic into the idle state. The bus state logic cannot be forced into

any other state. When the master is disabled, and after reset, the bus state logic is disabled and the bus state is

unknown.

BUSSTATE[1:0]

Group configuration

Description

UNKNOWN

Unknown bus state

IDLE

Idle bus state

OWNER

Owner bus state

BUSY

Busy bus state

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